Microprocessors are widely used to perform all manner of data processing functions. More sophisticated data processing applications involving large quantities of data, for example 3-D graphics processing, place ever increasing demands on the operational speeds of microprocessors. One approach to achieving higher speeds is to minimize the physical path lengths that signals must travel within the processor. Not only is it desirable to construct the entire processor on a single integrated circuit chip, but the critical path lengths on the chip should be minimized as well. Since chip processing techniques place practical limits on circuit dimensions, there is an inherent conflict between providing greater processor versatility (requiring more logic circuitry and hence more on-chip real estate) and providing higher speeds.
Since many data processing tasks involve a relatively few number of operations, but require that they be performed on large arrays of data, the conflict between speed and versatility in such applications is resolved in favor of speed by limiting the number of defined operations the processor can perform and limiting the size (in bits) of operands within the processor. A processor so optimized is commonly referred to as a reduced instruction set computer (RISC).
Although a RISC processor may be optimized to perform certain repetitive data processing tasks, it is desirable that the processor be able to perform an extended range of functions without undue degradation in performance. One approach to overcoming the limitations of a fixed instruction length is to prefix an instruction with another instruction such that operands can be constructed having a greater number of bits than can be specified by a single instruction. U.S. Pat. No. 4,724,517 issued to May describes a RISC processor in which an operand register concatenates values provided by a prefix instruction and a using instruction to accumulate a value of variable bit length. Separate prefix instructions are provided for positive and negative values. The operand is constructed in the operand register, and thus each occurrence of a using instruction must be immediately preceded by the appropriate prefix instruction(s).